1. Field of the Invention
This invention relates to a clock frequency divider which divides a frequency of a clock by an arbitrary value including an odd number, and a trigger signal generation circuit which supplies the clock frequency divider with a timing signal which fractionally divides the clock signal, and in particular, relates to a clock frequency divider which reduces the number of flip-flop stages and enables high-speed operation, and to a trigger generation circuit for same.
2. Description of the Related Art
A clock frequency divider divides a frequency of a reference clock signal by a prescribed division ratio, and generates a frequency-divided clock signal having a period which is a reference clock period multiplied by a frequency division value. General clock frequency dividers have a ring counter in which flip-flops are connected in a plurality of stages, and outputs the frequency-divided clock signal with a timing resulting by counting a reference clock pulses of the preset frequency division value. As a result of this configuration, the number of flip-flop stages is increased, a time until the output state of the counter circuit is finalized in response to changes in the reference clock signal is long, and high-frequency clock signals cannot be accommodated.
A clock frequency divider of the prior art has been proposed which is configured from two counters capable of counting up to N reference clock pulses, and a switching circuit which selects the outputs thereof, to generate a frequency-divided clock signal with a division ratio of 1/(N+0.5). See for example Japanese Patent Laid-open No. 53-76731.
A clock frequency divider has also been proposed in which a single counter circuit and a ½ frequency divider circuit are connected, and the counter is reset by logical operations on different counter outputs of the counter circuit and on the output of the frequency divider circuit, to generate a frequency-divided clock signal divided by an odd number. See for example Japanese Patent Laid-open No. 60-86918.
Further, a clock frequency divider has been proposed having a first counter which counts reference clock pulses and a second counter which counts inverted clock pulses of the reference clock signal, and which uses both counter outputs to generate a frequency-divided clock signal, frequency-divided by an odd number, with a duty ratio of 50%. See for example Japanese Patent Laid-open No. 63-3514.
Further, a clock frequency divider has been proposed in which two auxiliary counter circuits are provided, and data output terminals of two auxiliary counters are logically combined to generate an output clock signals, while in addition the auxiliary counters are reset by the output clock signal. This clock frequency divider is capable of a comparatively large number of division ratios. See for example Japanese Patent Laid-open No. 7-50576.
Further, a clock frequency divider has been proposed in which a counter which counts to N is used to count up to N, and an output signal is used for reset. See for example Japanese Patent Laid-open No. 5-347555.
Further, a clock frequency divider has been proposed in which two flip-flops are provided, operating on positive-phase and negative-phase clock signals, in the final stage of a counter which counts up to N. See for example Japanese Patent Laid-open No. 5-259895.
Clock frequency dividers proposed in the prior art have an operation speed capable of operating by fast reference clock signals, but cannot generate a frequency-divided clock signal at an arbitrary fractional division ratio by the reference clock signal. For example, when the division ratio is made larger than 2, a counting circuit in which a plurality of flip-flop stages are connected must be used. The counting circuit operates by fast clock signals, and performs counting operation by finalizing output values of a plurality of flip-flop stages. Consequently when the number of stages is large, the time from a change in the reference clock signal until output value finalization is correspondingly longer. Hence the counter circuit with the number of flip-flop stages cannot readily operate by the fast clock signal, and so it is desired that the number of flip-flop stages of the counter circuit be made as small as possible.
On the other hand, there are clock frequency dividers in which the counter circuit with a smaller maximum count value than the division ratio is used to generate a trigger signal, and this trigger signal is modified to generate the frequency-divided clock signal, as for example in Japanese Patent Laid-open No. 60-86918. However, when dividing by an even number in such the clock frequency divider, the trigger signal is generated with the timing at which N pulses of the reference clock signal are counted, and the trigger signal is generated with the timing at which (N+1) pulses are counted, and these trigger signals are used to generate a clock pulse frequency-divided by the odd number of (2N+1). However, a duty ratio of such the frequency-divided clock signal is not 50%. Because the frequency-divided clock signal with the duty ratio of 50% is suitable for various applications, it is desirable that the clock frequency divider generates the frequency-divided clock signal with the duty ratio of 50%.